Display substrate and display device thereof

ABSTRACT

The present disclosure relates to a display substrate, including: a substrate including a display region and a peripheral region surrounding the display region, the peripheral region including a first wiring region, the first wiring region including a first sub-wiring region disposed along a first direction away from the display region; a first conductive layer located on the substrate; a first dielectric layer located on the first conductive layer; a second conductive layer located on the first dielectric layer; a second dielectric layer located on the second conductive layer; a third conductive layer located on the second dielectric layer; a third dielectric layer as a planarization layer located on the third conductive layer; a fourth conductive layer located on the third dielectric layer. The fourth wiring is electrically connected to the third wiring. An orthographic projection of the fourth wiring on the substrate at least partially overlaps with an orthographic projection of the third wiring on the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is the U.S. National Stage Entry ofPCT/CN2020/134874, filed on Dec. 9, 2020, the entire disclosure of whichis incorporated herein by reference as part of the disclosure of thisapplication.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field of displayingtechnology, and particularly, relate to a display substrate and adisplay device thereof.

BACKGROUND

In recent years, as technologies and industries have further developed,Organic Light Emitting Diode (OLED) display panels have been widely usedin products such as mobile phones, wearable devices, computers, etc.

SUMMARY

Embodiments of the present disclosure provide a display substrate. Thedisplay substrate includes: a substrate comprising a display region anda peripheral region surrounding the display region, the peripheralregion comprising a first wiring region, the first wiring regioncomprising a first sub-wiring region disposed along a first directionaway from the display region; a first conductive layer located on thesubstrate, the first conductive layer comprising a first portion locatedin the peripheral region, the first portion of the first conductivelayer comprising a first wiring located in the first wiring region; afirst dielectric layer located on the first conductive layer; a secondconductive layer located on the first dielectric layer, the secondconductive layer comprising a first portion located in the peripheralregion, wherein the first portion of the second conductive layercomprises a second wiring located in the first wiring region, the firstwiring and the second wiring being spaced apart from each other along adirection parallel to the substrate; a second dielectric layer locatedon the second conductive layer; a third conductive layer located on thesecond dielectric layer, the third conductive layer comprising a firstportion located in the peripheral region, wherein the first portion ofthe third conductive layer comprises a third wiring located in the firstwiring region; a third dielectric layer as a planarization layer locatedon the third conductive layer; a fourth conductive layer located on thethird dielectric layer, the fourth conductive layer comprising a firstportion located in the peripheral region, the first portion of thefourth conductive layer comprising a fourth routing located in the firstsub-wiring region. The fourth wiring is electrically connected to thethird wiring. An orthographic projection of the fourth wiring on thesubstrate at least partially overlaps with an orthographic projection ofthe third wiring on the substrate.

In an embodiment of the present disclosure, the third dielectric layercomprises a first via exposing the third wiring located in the firstsub-wiring region. The fourth wiring is connected to the third wiringvia the first via.

In an embodiment of the present disclosure, the third wiring and thefourth wiring constitute a first power signal line.

In an embodiment of the present disclosure, the first via comprises afirst array of first sub-vias and a second array of second sub-vias, thefirst sub-vias and the second sub-vias being configured such that atleast one of the first sub-vias is surrounded by the second sub-viasclosest to the at least one first sub-via, and at least one of thesecond sub-vias is surrounded by the first sub-vias closest to the atleast one second sub-via.

In an embodiment of the present disclosure, at least one of the firstsub-vias is located at a center of a shape enclosed by the secondsub-vias closest to the at least one first sub-via, and at least one ofthe second sub-vias is located at a center of a shape enclosed by thefirst sub-vias closest to the at least one second sub-via.

In an embodiment of the present disclosure, a cross-sectional shape ofthe first via along a plane parallel to the substrate comprises atruncated square.

In an embodiment of the present disclosure, a side of the truncatedsquare has a length of 11 μm.

In an embodiment of the present disclosure, the first portion of thefourth conductive layer comprises a second via exposing the thirddielectric layer.

In an embodiment of the present disclosure, the second via comprises afirst array of third sub-vias and a second array of fourth sub-vias. Thethird sub-vias and the fourth sub-vias are configured such that at leastone of the third sub-vias is surrounded by the fourth sub-vias closestto the at least one third sub-via, and at least one of the fourthsub-vias is surrounded by the third sub-vias closest to the at least onefourth sub-via.

In an embodiment of the present disclosure, at least one of the thirdsub-vias is located at a center of a shape enclosed by the fourthsub-vias closest to the at least one third sub-via. At least one of thefourth sub-vias is located at a center of a shape enclosed by the thirdsub-vias closest to the at least one fourth sub-via.

In an embodiment of the present disclosure, a cross-sectional shape ofthe second via along a plane parallel to the substrate comprises asquare.

In an embodiment of the present disclosure, a side of the square has alength of 16 μm.

In an embodiment of the present disclosure, at least one of the firstvias is located at a center of a shape enclosed by the second viasclosest to the at least one first via. At least one of the second viasis located at a center of a shape enclosed by the first vias closest tothe at least one second via.

In an embodiment of the present disclosure, a spacing located betweenthe first via and the second via is 6.5 μm in the first direction. Aspacing located between the first via and the second via is 16.5 μm in asecond direction parallel to the substrate and perpendicular to thefirst direction.

In an embodiment of the present disclosure, the display substratefurther comprises a thin film transistor located in the display region,the thin film transistor comprising an active layer located on thesubstrate, a gate insulating layer located on the active layer, and agate located on the gate insulating layer. The first conductive layerfurther comprises a second portion located in the display region. Thesecond portion of the first conductive layer comprising the gate of thethin film transistor. The third conductive layer further comprises asecond portion located in the display region. The second portion of thethird conductive layer comprising a source/drain electrode of the thinfilm transistor. The source/drain electrode is connected to asource/drain region of the active layer by passing through the firstdielectric layer, the second dielectric layer, and the gate insulatinglayer.

In an embodiment of the present disclosure, the fourth conductive layerfurther comprises a second portion located in the display region. Thesecond portion of the fourth conductive layer is connected to thesource/drain electrode of the thin film transistor by passing throughthe third dielectric layer.

In an embodiment of the present disclosure, the display substratefurther comprises a fourth dielectric layer as a planarization layerlocated on the fourth conductive layer; and an encapsulation layerlocated on the fourth dielectric layer.

In an embodiment of the present disclosure, the display substratefurther comprises a light emitting device located in the display regionand located between the fourth dielectric layer and the encapsulationlayer. The light emitting device comprises an anode, a light emittinglayer, and a cathode sequentially disposed along a directionperpendicular to the substrate. The anode is located between the fourthdielectric layer and the encapsulation layer. The anode is connected tothe second portion of the fourth conductive layer via a via located inthe fourth dielectric layer. The display substrate further comprises apixel definition layer defining a light emitting region located betweenthe fourth dielectric layer and the encapsulation layer. The pixeldefinition layer has an opening exposing the anode.

In an embodiment of the present disclosure, the first wiring regionfurther comprises a second sub-wiring region located on a side of thefirst sub-wiring region away from the display region. The displaysubstrate further comprises a dam located in the second sub-wiringregion, the dam comprising a first dam portion and a second dam portionsequentially spaced apart along a direction away from the displayregion. The first dam portion comprises the fourth dielectric layer andthe pixel definition layer. The second dam portion comprises the thirddielectric layer, the fourth dielectric layer, and the pixel definitionlayer.

In an embodiment of the present disclosure, the peripheral regionfurther comprises a bending region and a second wiring regionsequentially arranged in the first direction away from the displayregion and on a side of the first wiring region away from the displayregion. The bending region has an opening passing through the gateinsulating layer, the first dielectric layer, and the second dielectriclayer and exposing the substrate, and a planarization layer covering theopening. The planarization layer comprises at least one of the thirddielectric layer and the fourth dielectric layer. The second wiringregion comprises the gate insulating layer, the first dielectric layer,the second dielectric layer, the third conductive layer, the fourthconductive layer, and the fourth dielectric layer sequentially disposedon the substrate along a direction perpendicular to the substrate.

In an embodiment of the present disclosure, the display substratefurther comprises a second power signal line located in the peripheralregion and surrounding the display region and the first power signalline. The second power signal line comprises at least one of a portionof the third conductive layer located in the peripheral region and aportion of the fourth conductive layer located in the peripheral region.The first power signal line is configured to provide a first voltage.The second power signal line is configured to provide a second voltage.The first voltage is higher than the second voltage.

In an embodiment of the present disclosure, the display substratefurther comprises a passivation layer located between the thirdconductive layer and the third dielectric layer.

In an embodiment of the present disclosure, an orthographic projectionof the first wiring on the substrate at least partially overlaps with anorthographic projection of the first via and the second via on thesubstrate. An orthographic projection of the second wiring on thesubstrate at least partially overlaps with an orthographic projection ofthe first via and the second via on the substrate.

In an embodiment of the present disclosure, the encapsulation layersequentially covers the first sub-wiring region and the dam in adirection parallel to the substrate and away from the display region. Atleast a portion of an edge of the encapsulation layer is located withinthe second sub-wiring region.

In an embodiment of the present disclosure, the first power signal linefurther comprises a portion located in the second sub-wiring region, thebending region, and the second wiring region and disposed in the samelayer as the third conductive layer and/or the fourth conductive layer.

Embodiments of the present disclosure provide a display device. Thedisplay device includes the display substrate as described above.

Further aspects and areas of applicability will become apparent from thedescription provided herein. It should be understood that variousaspects of the present application may be implemented individually or incombination with one or more other aspects. It should also be understoodthat the description and specific examples herein are intended forpurposes of illustration only and are not intended to limit the scope ofthe present application.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are for illustrative purposes only ofselected embodiments and not all possible implementations, and are notintended to limit the scope of the present application.

FIG. 1 illustrates a portion of a schematic cross-sectional view of aperipheral region of a display substrate.

FIG. 2 illustrates a schematic plan view of a display substrate inaccordance with an embodiment of the present disclosure.

FIG. 3 illustrates a schematic cross-sectional view of a displaysubstrate taken along line aa′ in FIG. 2 in accordance with anembodiment of the present disclosure.

FIG. 4 illustrates a schematic view of a plan arrangement of a first viain accordance with an embodiment of the present disclosure.

FIG. 5 illustrates a schematic view of a plan arrangement of a secondvia in accordance with an embodiment of the present disclosure.

FIG. 6 illustrates a schematic view of a plan arrangement of the firstvia and the second via in accordance with an embodiment of the presentdisclosure.

FIG. 7 illustrates an enlarged schematic plan view of the portion bb′ inFIG. 2 in accordance with an embodiment of the present disclosure.

FIG. 8 illustrates an enlarged schematic plan view of portion cc′ inFIG. 2 in accordance with an embodiment of the present disclosure.

FIG. 9 illustrates a schematic plan view of a display device inaccordance with an embodiment of the present disclosure.

Corresponding reference numerals indicate corresponding parts orfeatures throughout the several diagrams of the drawings.

DETAILED DESCRIPTION

Firstly, it should be noted that, as used herein and in the appendedclaims, the singular form of a word includes the plural, and vice versa,unless the context clearly dictates otherwise. Thus, the references “a”,“an”, and “the” are generally inclusive of the plurals of the respectiveterms. Similarly, the words “comprise”, “comprises”, and “comprising”are to be interpreted inclusively rather than exclusively. Likewise, theterms “include”, “including” and “or” should all be construed to beinclusive, unless such a construction is clearly prohibited from thecontext. The term “example” used herein, particularly when followed by alisting of terms, is merely exemplary and illustrative and should not bedeemed to be exclusive or comprehensive.

Additionally, further to be noted, when the elements and the embodimentsthereof of the present application are introduced, the articles “a/an”,“one”, “the” and “said” are intended to represent the existence of oneor more elements. Unless otherwise specified, “a plurality of” means twoor more. The expressions “comprise”, “include”, “contain” and “have” areintended as inclusive and mean that there may be other elements besidesthose listed. The terms such as “first” and “second” are used hereinonly for purposes of description and are not intended to indicate orimply relative importance and the order of formation.

In addition, it should be noted that, in the description of the presentdisclosure, the orientations or positions relationship indicated by theterms “upper”, “above”, “lower”, “under”, “top”, “bottom”, “between”,etc. are the orientations or positions relationship based on theorientations or positions relationship shown in the drawings, which ismerely for the convenience of describing the present disclosure andsimplifying the description, and does not indicate or imply that thereferred device or element has to have a specific orientation and isconstructed and operated in a specific orientation, therefore, it can'tbe understood as a limitation to the disclosure. In addition, when anelement or a layer is referred to as being “on” another element orlayer, the element or the layer can be directly on the another elementor layer, or an intermediate element or layer can be present; likewise,when an element or a layer is referred to as being “under” anotherelement or layer, the element or the layer can be directly under anotherelement or layer, or at least one intermediate element or layer can bepresent; when an element or a layer is referred to as being between twoelements or two layers, the element or the layer can be an uniqueelement or layer between the two elements or the two layers, or morethan one intermediate element or layer can be present.

Exemplary embodiments will now be described more fully with reference tothe accompanying drawings.

At present, due to an increase in pixels per inch (PPI) of a displaysubstrate, wirings in a peripheral region of the display substratebecome more and more, and the wiring layout is complex. As a result, anoverlying film layer within a wiring region is extremely not flat. Inthis case, when a chemical vapor deposition (CVD) film is used forencapsulation, the CVD film, which is the overlying film layer, issusceptible to poorly contact with an underlying film layer, resultingin poor encapsulation. It should be understood that the underlying filmlayer refers to a single layer or multi-layer film layer formed prior tothe overlying film layer.

In particular, FIG. 1 illustrates a portion of a schematiccross-sectional view of a peripheral region of a display substrate. Asshown in FIG. 1, the display substrate includes a substrate 100, a firstwiring 131 and a second wiring 151 located on the substrate 100, anencapsulation layer (including a CVD film layer) 250 located on thefirst wiring 131 and the second wiring 151, and a laminated structure 20located between the first wiring 131 and the second wiring 151 and theencapsulation layer 250. The film layers included in the laminatedstructure 20 are all conformal. It should be noted that, “conformal”described herein refers to that a surface shape of a formed film layeris consistent or substantially the same as a surface shape of astructure located below the formed film layer. Because the wirings inthe peripheral region are more and an arrangement of the wirings iscomplicated, for example, a spacing located between the first wiring 131and the second wiring 151 is small. Thus, when forming the encapsulationlayer 250, the encapsulation layer 250 is prone to poorly contact withthe underlying film layer (e.g., the laminated structure 20, etc.) at alocation A. For example, a portion of the encapsulation layer 250 atlocation A is not in contact with the underlying film layer. As aresult, poor encapsulation is further caused.

Embodiments of the present disclosure provide a display substratecapable of improving the flatness of wirings in the peripheral regionand significantly avoiding poor contact between the encapsulation layerand the underlying film layer occurring in the peripheral region, suchthat the encapsulation layer is in good contact with the underlying filmlayer, thereby avoiding encapsulation defect and improving productyield.

FIG. 2 illustrates a schematic plan view of a display substrate inaccordance with an embodiment of the present disclosure. As shown inFIG. 2, the display substrate 10 may include a substrate 100. Thesubstrate 100 may include a display region AA and a peripheral regionsurrounding the display region AA. The display substrate 10 may alsoinclude a dam 300 surrounding the display region AA, located on thesubstrate 100 and located in the peripheral region.

Other illustrated portions of FIG. 2 will be described with reference toFIG. 3. In addition, the display substrate of the embodiments of thepresent disclosure will be further described with reference to FIG. 3.

It should be noted that the drawing dimensions of FIGS. 2 and 3, as wellas the distances between the various regions or components as shown, arefor the purpose of illustrating embodiments of the present disclosureand are merely exemplary. It will be appreciated by those skilled in theart that the dimension, spacing, etc. may be adjusted depending on theneeds and product design when applied.

FIG. 3 illustrates a schematic cross-sectional view of the displaysubstrate taken along line AA′ in FIG. 2 in accordance with anembodiment of the present disclosure. As shown in FIG. 3, the displaysubstrate 10 may include the substrate 100. As described above, thesubstrate 100 may include the display region AA and the peripheralregion surrounding the display region AA. In an embodiment of thepresent disclosure, the peripheral region may include a first wiringregion BB. As an example, the first wiring region BB may be, forexample, a first fanout region.

In an exemplary embodiment of the present disclosure, the first wiringregion BB may include a first sub-wiring region BB′ and a secondsub-wiring region BB″ sequentially disposed along a first direction Xaway from the display region AA.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a first conductive layer 130 located on the substrate100. The first conductive layer 130 may include a first portion 131located in the peripheral region. As an example, the first portion 131of the first conductive layer 130 may include a first wiring (alsodenoted by reference numeral 131) located in the first wiring region BB.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a first dielectric layer 140 located on the firstconductive layer 130. In an exemplary embodiment of the presentdisclosure, the first dielectric layer 140 may be conformal. As anexample, the first dielectric layer 140 may include an inorganic layer.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a second conductive layer 150 located on the firstdielectric layer 140. The second conductive layer 150 may include afirst portion 151 located in the peripheral region. As an example, thefirst portion 151 of the second conductive layer 150 may include asecond wiring (also denoted by reference numeral 151) located in thefirst wiring region BB.

In an embodiment of the present disclosure, the first wiring 131 and thesecond wiring 151 are spaced apart from each other along a directionparallel to the substrate 100 (e.g., the first direction X).

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a second dielectric layer 160 located on the secondconductive layer 150. In an exemplary embodiment of the presentdisclosure, the second dielectric layer 160 may be conformal. As anexample, the second dielectric layer 160 may include an interlayerdielectric layer. For example, the second dielectric layer 160 mayinclude an inorganic layer.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a third conductive layer 170 located on the seconddielectric layer 160. The third conductive layer 170 may include a firstportion 171 located in the peripheral region. As an example, the firstportion 171 of the third conductive layer 170 may include a third wiring(also denoted by reference numeral 171) located in the first wiringregion BB.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a third dielectric layer 180 as a planarization layerlocated on the third conductive layer 170. In an embodiment of thepresent disclosure, the third dielectric layer 180 is provided toimprove the flatness of the wirings located within the peripheral regionof the display substrate 10. More specifically, because, for example,the spacing located between the first wiring 131 and the second wiring151 is small and the overlying film layer is conformal, a surface of theresulting structure is not flat. In contrast, the embodiments of thepresent disclosure provide the third dielectric layer 180 as aplanarization layer over the first wiring 131 and the second wiring 151and thus obtain a structure surface with improved flatness, facilitatingeffective contact between the subsequent encapsulation layer and theunderlying structure, and thereby improving the encapsulation effect.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a fourth conductive layer 190 located on the thirddielectric layer 180. The fourth conductive layer 190 may include afirst portion 191 located in the peripheral region. As an example, thefirst portion 191 of the fourth conductive layer 190 may include afourth wiring (also denoted by reference numeral 191) located in thefirst sub-wiring region BB′. In an exemplary embodiment of the presentdisclosure, the fourth wiring 191 may be electrically connected to thethird wiring 171. In an exemplary embodiment of the present disclosure,an orthographic projection of the fourth wiring 191 on the substrate 100at least partially overlaps with an orthographic projection of the thirdwiring 171 on the substrate 100.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a fourth dielectric layer 200 as a planarization layerlocated on the fourth conductive layer 190. As an example, the fourthdielectric layer 200 may include an organic layer.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include an encapsulation layer 250 located on the fourthdielectric layer 200. As an example, the encapsulation layer 250 may bea film layer formed by chemical vapor deposition.

In an embodiment of the present disclosure, the third dielectric layer170 may include a first via H1 located in the first sub-wiring regionBB′ and exposing the third wiring 171. Further, the fourth wiring 191may be connected to the third wiring 171 via the first via H1. Thus, theresistance of a wiring formed by the third wiring 171 and the fourthwiring 191 is lower, thereby having better electrical performance.

In an embodiment of the present disclosure, the first via H1 may alsopenetrate through a passivation layer (not shown).

In an exemplary embodiment of the present disclosure, the third wiring171 and the fourth wiring 191 may constitute at least a portion of afirst power signal line VDD (as shown in FIG. 2).

In other exemplary embodiments of the present disclosure, referring toFIGS. 2 and 3, within the first sub-wiring region BB′, at least aportion of the first power signal line VDD may be composed of the thirdwiring 171 and the fourth wiring 191. Within a second sub-wiring regionBB′ (described later) of the first wiring region BB, at least a portionof the first power line VDD may be composed of the third wiring 171.

An example arrangement of the first via H1 is described below withreference to FIG. 4. It should be understood that the illustration ofFIG. 4 is merely a portion of the schematic diagram and is merelyexemplary, so as to clearly illustrate embodiments of the presentdisclosure and should not be taken as a limit to the disclosure.

FIG. 4 illustrates a schematic view of a plan arrangement of the firstvia in accordance with an embodiment of the present disclosure. As shownin FIG. 4, in an embodiment of the present disclosure, the first via H1may include a first array of first sub-vias H1′ and a second array ofsecond sub-vias H1″. In an exemplary embodiment of the presentdisclosure, the first sub-vias H1′ and the second sub-vias H1″ may beconfigured such that at least one of the first sub-vias H1′ may besurrounded by the second sub-vias H1″ closest to the at least one firstsub-via H1′, and at least one of the second sub-vias H1″ may besurrounded by the first sub-vias H1′ closest to the at least one secondsub-via H1″.

In an exemplary embodiment of the present disclosure, at least one ofthe first sub-vias H1′ may be located at a center of a shape (e.g., theshape may be a square) enclosed by the second sub-vias H1″ closest tothe at least one first sub-via H1′. At least one of the second sub-viasH1″ may be located at a center of a shape (e.g., the shape may be asquare) enclosed by the first sub-vias H1′ closest to the at least onesecond sub-via H1″.

In an embodiment of the present disclosure, the position arrangement ofthe first sub-via and the second sub-via as described above can meet theflatness requirement to the overlying film layer, and can facilitate theelectrical contact between the third wiring 171 and the fourth wiring191. It should be understood that those skilled in the art will be ableto set the distribution density and dimension of the first sub-via andthe second sub-via as desired, e.g., flatness requirements andelectrical characteristic requirements, which are not specificallylimited herein.

In an exemplary embodiment of the present disclosure, a cross-sectionalshape of the first via H1 along a plane parallel to the substrate 100may include, for example, a truncated square, as shown in FIG. 4.

In an exemplary embodiment of the present disclosure, a side of thetruncated square may have a length d1 of 11 μm. Note that, the lengthrefers to a length of a side of the square before being truncated.

It should be noted that the dimensions of the sub-vias and the spacinglocated between the sub-vias shown in FIG. 4 are merely exemplary inorder to clearly illustrate embodiments of the present disclosure andare not to be considered a limit to the present disclosure. It will beappreciated that the spacing located between the sub-vias may be shownto be larger or smaller.

Referring to FIG. 3 again, in an embodiment of the present disclosure,the first portion 191 of the fourth conductive layer 190 may include asecond via H2 exposing the third dielectric layer 180. In an embodimentof the present disclosure, the second via H2 is used for discharging gasremained within the third dielectric layer 180 when the third dielectriclayer 180 is formed, otherwise the gas may damage the structural layerof the display substrate, e.g., causing peeling-off, stripping-off, etc.of the first portion 191 of the fourth conductive layer 190 from theunderlying film layer.

In an exemplary embodiment of the present disclosure, the third wiring171 and the fourth wiring 191 may constitute at least a portion of thefirst power signal line VDD (as shown in FIG. 2). In an exemplaryembodiment of the present disclosure, an orthographic projection of thesecond via H2 on the substrate 100 at least partially overlaps with anorthographic projection of the first power signal line VDD on thesubstrate 100.

An example arrangement of the second via H2 is described below withreference to FIG. 5. It should be understood that the illustration ofFIG. 5 is merely a portion of the schematic diagram and is merelyexemplary, so as to clearly illustrate embodiments of the presentdisclosure and should not be taken as a limit to the disclosure.

FIG. 5 illustrates a schematic view of a plan arrangement of the secondvia in accordance with an embodiment of the present disclosure. As shownin FIG. 5, in an embodiment of the present disclosure, the second via H2may include a first array of third sub-vias H2′ and a second array offourth sub-vias H2″. In an exemplary embodiment of the presentdisclosure, the third sub-vias H2′ and the fourth sub-vias H2″ may beconfigured such that at least one of the third sub-vias H2′ may besurrounded by the fourth sub-vias H2″ closest to the at least one thirdsub-via H2′, and at least one of the fourth sub-vias H2″ may besurrounded by the third sub-vias H2′ closest to the at least one fourthsub-via H2″.

In an exemplary embodiment of the present disclosure, at least one ofthe third sub-vias H2′ may be located at a center of a shape (e.g., theshape may be a square) enclosed by the fourth sub-vias H2″ closest tothe at least one third sub-via H2′. At least one of the fourth sub-viasH2″ may be located at a center of a shape (e.g., the shape may be asquare) enclosed by the third sub-vias H2′ closest to the at least onefourth sub-via H2″.

In an embodiment of the present disclosure, the position arrangement ofthe third sub-via and the fourth sub-via as described above can achievea good electrical effect, for example, obtain a reduced resistance ofthe fourth wiring 191. It should be understood that those skilled in theart will be able to set the distribution density and dimension of thethird sub-via and the fourth sub-via as desired, e.g., electricalcharacteristic requirements, which are not specifically limited herein.

In an exemplary embodiment of the present disclosure, a cross-sectionalshape of the second via H2 along a plane parallel to the substrate 100may include, for example, a square, as shown in FIG. 5.

In an exemplary embodiment of the present disclosure, a side of thesquare may have a length d2 of 16 μm.

It should be noted that the dimensions of the sub-vias and the spacinglocated between the sub-vias shown in FIG. 5 are merely exemplary inorder to clearly illustrate embodiments of the present disclosure andare not to be considered a limit to the present disclosure. It will beappreciated that the spacing located between the sub-vias may be shownto be larger or smaller. In addition, it is to be understood that theshapes of the sub-vias shown in the figures are merely exemplary. Forexample, when the sub-vias are designed to be square, due to thelimitations of the actual process, the sub-via obtained after the actualmanufacturing process may have a shape of chamfer (e.g., an includedangle between adjacent sides less than or greater than 90 degrees).

An example arrangement of the first via H1 and the second via H2 isdescribed below with reference to FIG. 6. It should be understood thatthe illustration of FIG. 6 is merely a portion of the schematic diagramand is merely exemplary, so as to clearly illustrate embodiments of thepresent disclosure and should not be taken as a limit to the disclosure.

FIG. 6 illustrates a schematic view of a plan arrangement of the firstvia and the second via in accordance with an embodiment of the presentdisclosure. As shown in FIG. 6, in an exemplary embodiment of thepresent disclosure, at least one of the first vias H1 may be located ata center of a shape enclosed by the second vias H2 closest to the atleast one first via H1. At least one of the second vias H2 may belocated at a center of a shape enclosed by the first vias H1 closest tothe at least one second via H2. With this arrangement, the portion ofthe third dielectric layer 180 located between the first vias H1 issufficiently discharged of gas.

In an embodiment of the present disclosure, the positional relationshipbetween the first via and the second via is beneficial for the dischargeof moisture contained in the third dielectric layer 180 during theprocess of preparing the third dielectric layer 180, thereby enablinghigher yield products. By way of example, the second via H2 may bedisposed at a center of a shape enclosed by the surrounding first viasH1 as disclosed in the embodiment of the present disclosure, so as tocompletely discharge the moisture contained in the third dielectriclayer 180 as much as possible. It should be understood that, in oneaspect, those skilled in the art can design the position, distributiondensity and dimension of the first via H1 according to actual needs,such as flatness requirements and electrical characteristicrequirements; on the other hand, those skilled in the art can design theposition, distribution density and dimension of the second via H2according to actual needs, such as moisture discharging requirements,and the plan arrangement of the first via H1, which is not specificallylimited herein.

In an exemplary embodiment of the present disclosure, in the firstdirection X, a spacing d3 located between the first via H1 and thesecond via H2 may be, for example, 6.5 μm. In a second direction Yparallel to the substrate 100 and perpendicular to the first directionX, a spacing d4 located between the first via H1 and the second via H2may be, for example, 16.5 μm.

Referring again to FIG. 3, in an embodiment of the present disclosure,the display substrate 10 may further include a thin film transistor TFTlocated in the display region AA. In an exemplary embodiment of thepresent disclosure, the thin film transistor TFT may include an activelayer 110 located on the substrate 100, a gate insulating layer 120located on the active layer 110, and a gate 132′ located on the gateinsulating layer 120.

In an embodiment of the present disclosure, the first conductive layer130 may further include a second portion 132 located in the displayregion AA. In an exemplary embodiment of the present disclosure, thesecond portion 132 of the first conductive layer 130 may include thegate 132′ of the thin film transistor TFT. In an exemplary embodiment ofthe present disclosure, the second portion 132 of the first conductivelayer 130 may also include a first electrode 132″ of a capacitor.

In an embodiment of the present disclosure, the second conductive layer150 may further include a second portion 152 located in the displayregion AA. As an example, the second portion 152 of the secondconductive layer 150 may include a second electrode (also denoted byreference numeral 152) of the capacitor described above.

It should be understood that the capacitor described above may beconfigured similar to the capacitor in a conventional pixel drivingcircuit. Other descriptions regarding capacitor are known in the art andwill not be repeated herein.

In an embodiment of the present disclosure, the third conductive layer170 may further include a second portion 172 located in the displayregion AA. In an exemplary embodiment of the present disclosure, thesecond portion 172 of the third conductive layer 170 may include asource/drain electrode (also denoted by reference numeral 172) of thethin film transistor TFT. In an exemplary embodiment of the presentdisclosure, the source/drain electrodes 172 may be connected to asource/drain region of the active layer 110 by sequentially passingthrough the second dielectric layer 160, the first dielectric layer 140,and the gate insulating layer 120.

In an embodiment of the present disclosure, the fourth conductive layer190 may further include a second portion 192 located in the displayregion AA. In an exemplary embodiment of the present disclosure, thesecond portion 192 of the fourth conductive layer 190 is connected tothe source/drain electrode 172 of the thin film transistor TFT bypassing through the third dielectric layer 180. As an example, thesecond portion 192 of the fourth conductive layer 190 may serve as apower signal line in order to control the operation of the thin filmtransistor. For example, the power signal line may input a high voltageor a low voltage.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a light emitting device OLED located in the displayregion AA and located between the fourth dielectric layer 200 and theencapsulation layer 250. In an exemplary embodiment of the presentdisclosure, the light emitting device OLED may include an anode 210, alight emitting layer 230, and a cathode 240 sequentially disposed alonga third direction Z perpendicular to the substrate 100. In particular,the anode 210 may be located between the fourth dielectric layer 200 andthe encapsulation layer 250. Further, the anode 210 may be connected tothe second portion 192 of the fourth conductive layer 190 via a thirdvia H3 in the fourth dielectric layer 200.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a pixel definition layer 220 defining a light emittingregion located between the fourth dielectric layer 200 and theencapsulation layer 250. In an exemplary embodiment of the presentdisclosure, the pixel definition layer 220 may have an opening O1exposing the anode 210 of the light emitting device OLED.

Referring to FIGS. 2-3, in an embodiment of the present disclosure, thedisplay substrate 10 may further include a dam 300 located in the secondsub-wiring region BB″. In particular, the dam 300 surrounds the displayregion AA. The dam 300 may, for example, prevent water and oxygen fromentering the display region AA.

In an embodiment of the present disclosure, referring to FIG. 3, in adirection parallel to the substrate 100 and away from the display regionAA (e.g., the X-direction), the encapsulation layer 250 may sequentiallycover the first sub-wiring region BB′ and the dam 300, and at least aportion of an edge of the encapsulation layer 250 may be located withinthe second sub-wiring region BB″.

With continued reference to FIG. 3, in an exemplary embodiment of thepresent disclosure, the dam 300 may at least include a first dam portion300′ and a second dam portion 300″ sequentially spaced apart along thefirst direction X away from the display region AA.

In an exemplary embodiment of the present disclosure, the first damportion 300′ may include the fourth dielectric layer 200 and the pixeldefinition layer 220. Specifically, the first dam portion 300′ mayinclude, for example, a portion 201 of the fourth dielectric layer 200located in the second sub-wiring region BB″ and a portion 221 of thepixel definition layer 220 located in the second sub-wiring region BB″.As shown in FIG. 3, the portion 221 of the pixel definition layer 220may cover a portion of the first portion 171 of the third conductivelayer 170 and the portion 201 of the fourth dielectric layer 200.

In an exemplary embodiment of the present disclosure, the second damportion 300″ may include the third dielectric layer 180, the fourthdielectric layer 200 and the pixel definition layer 220. Specifically,the second dam portion 300′ may include, for example, a portion 181 ofthe third dielectric layer 180 located in the second sub-wiring regionBB″, a portion 202 of the fourth dielectric layer 200 located in thesecond sub-wiring region BB″ and a portion 222 of the pixel definitionlayer 220 located in the second sub-wiring region BB″. As shown in FIG.3, the portion 202 of the fourth dielectric layer 200 may cover thefirst portion 171 of the third conductive layer 170 and the portion 181of the third dielectric layer 181. The portion 222 of the pixeldefinition layer 220 may cover the first portion 171 of the thirdconductive layer 170 and the portion 202 of the fourth dielectric layer200.

It should be understood that the film layers and laminatingrelationships of the first dam portion 300′ and the second dam portion300″ are exemplary only. For example, the first dam portion 300′ and thesecond dam portion 300″ may include more film layers or less filmlayers. Optionally, the dam 300 includes, for example, only one of thefirst dam portion 300′ and the second dam portion 300″. It is to beunderstood that the illustration of FIG. 3 is intended to clearlyillustrate embodiments of the present disclosure and should not be takenas a limit to the disclosure.

With continued reference to FIGS. 2-3, in an embodiment of the presentdisclosure, the peripheral region of the display substrate 10 mayfurther include a bending region CC and a second wiring region DDsequentially arranged in the first direction X away from the displayregion AA and on a side of the first wiring region BB away from thedisplay region AA. As an example, the second wiring region DD may be,for example, a second fanout region.

Referring to FIG. 3, in an exemplary embodiment of the presentdisclosure, the bending region CC may have an opening O2 passing throughthe gate insulating layer 120, the first dielectric layer 180, and thesecond dielectric layer 200 and exposing the substrate 100 and aplanarization layer 260 covering the opening O2. For example, as shownin FIG. 3, the planarization layer 260 may also cover the first portion171 and the second dielectric layer 160 of the third conductive layer170.

In an exemplary embodiment of the present disclosure, the planarizationlayer 260 may include at least one of the third dielectric layer 180 andthe fourth dielectric layer 200. More specifically, the planarizationlayer 260 may include at least one of a portion of the third dielectriclayer 180 located in the bending region CC and a portion of the fourthdielectric layer 200 located in the bending region CC.

In an exemplary embodiment of the present disclosure, the second wiringregion DD may include the gate insulating layer 120, the firstdielectric layer 140, the second dielectric layer 160, the thirdconductive layer 170, the fourth conductive layer 190, and the fourthdielectric layer 200 sequentially disposed on the substrate 100 along athird direction Z perpendicular to the substrate 100.

More specifically, in an exemplary embodiment of the present disclosure,the second wiring region DD may include a portion of the gate insulatinglayer 120 located in the second wiring region DD, a portion of the firstdielectric layer 140 located in the second wiring region DD, a portionof the second dielectric layer 160 located in the second wiring regionDD, a third portion 173 of the third conductive layer 170 located in thesecond wiring region DD, a third portion 193 of the fourth conductivelayer 190 located in the second wiring region DD, and a portion 203 ofthe fourth dielectric layer 200 located in the second wiring region DD.

With continued reference to FIG. 2, in an embodiment of the presentdisclosure, the display substrate 10 may further include a second powersignal line VSS located in the peripheral region and surrounding thedisplay region AA and the first power signal line VDD.

In an exemplary embodiment of the present disclosure, further, thesecond power signal line VSS may include at least one of a portion ofthe third conductive layer 170 located in the peripheral region and aportion of the fourth conductive layer 190 located in the peripheralregion.

In an exemplary embodiment of the present disclosure, the first powersignal line VDD may be configured to provide a first voltage. The secondpower signal line VSS may be configured to provide a second voltage. Asan example, the first voltage may be higher than the second voltage, forexample. It should be noted that the high and low here represent onlythe relative magnitude relationship between the voltages of the inputs.

In an embodiment of the present disclosure, optionally, the first powersignal line VDD may further include a portion located in the secondsub-wiring region BB″, the bending region CC, and the second wiringregion DD and disposed in the same layer as the third conductive layer170 and/or the fourth conductive layer 190. For the description about“disposed in the same layer”, reference may be made to the correspondingdescriptions above, and will not be repeated herein.

As an example, the first power signal line VDD may further include aportion located in the second sub-wiring region BB″, the bending regionCC, and the second wiring region DD and disposed in the same layer asthe third conductive layer 170.

As another example, the first power signal line VDD may further includea portion located in the second sub-wiring region BB″, the bendingregion CC, and the second wiring region DD and disposed in the samelayer as the fourth conductive layer 190.

As yet another example, the first power signal line VDD may furtherinclude a portion located in the second sub-wiring region BB″, thebending region CC, and the second wiring region DD and disposed in thesame layer as the third conductive layer 170 and the fourth conductivelayer 190. In this case, the corresponding portion disposed in the samelayer as the third conductive layer 170 and the corresponding portiondisposed in the same layer as the fourth conductive layer 190 may beelectrically connected via a via, so as to provide the desiredelectrical performance.

In an embodiment of the present disclosure, the display substrate 10 mayfurther include a passivation layer (not shown) located between thethird conductive layer 170 and the third dielectric layer 180. In anexemplary embodiment of the present disclosure, the passivation layermay be conformal. As an example, the passivation layer may include aninorganic layer. It should be understood that the formation of apassivation layer on the third conductive layer 170 may preventprecipitation of materials such as metals that constitute the thirdconductive layer 170, thereby ensuring the quality of the product.

Details of portion bb′ and portion cc′ in FIG. 2 will be described belowwith reference to FIGS. 7-8.

FIG. 7 illustrates an enlarged schematic plan view of the portion bb′ inFIG. 2 in accordance with an embodiment of the present disclosure.Referring to FIGS. 2 and 7, FIG. 7 illustrates a portion of a planlayout of the peripheral region of the display substrate 10. Morespecifically, FIG. 7 illustrates a portion of a plan layout of the firstwiring region BB in the peripheral region of the display substrate 10.

In an exemplary embodiment of the present disclosure, at least a portionof the first power signal line VDD may span an region provided with thethird dielectric layer 180. For example, at least a portion of the firstpower signal line VDD may be located between a boundary 180′ of thethird dielectric layer 180 close to the display region AA and a boundary180″ of the third dielectric layer 180 away from the display region AA.

In an exemplary embodiment of the present disclosure, referring to FIG.7, the first wiring 131 and the second wiring 151 may span the boundary180′ of the third dielectric layer 180.

In an exemplary embodiment of the present disclosure, the first wiring131 and the second wiring 151 may also span portions of the first via H1and the second via H2.

In an exemplary embodiment of the present disclosure, referring to FIGS.2-3 and 7, an orthographic projection of the first wiring 131 on thesubstrate 100 may at least partially overlap with an orthographicprojection of the first via H1 and the second via H2 on the substrate100.

In an exemplary embodiment of the present disclosure, an orthographicprojection of the second wiring 151 on the substrate 100 may at leastpartially overlap with the orthographic projection of the first via H1and the second via H2 on the substrate 100.

In an exemplary embodiment of the present disclosure, the first wiring131 may be electrically connected to a data line in the display region.As an example, the data line may be disposed in the same layer as thesource/drain electrode 172 of the thin film transistor TFT. For example,the first wiring 131 may be electrically connected to the data line viaa via located in the first dielectric layer 140 and the seconddielectric layer 160. Here, “disposed in the same layer” refers to theformation by the same film layer at the same step. It should be notedthat “the same film layer” in an embodiment of the present disclosuremay refer to a film layer located on the same structural layer.Alternatively, for example, the film layer at the same level may be afilm layer formed to have a particular pattern by using the samefilm-forming process. The film layer may then be patterned by onepatterning process using the same mask to form the desired layerstructure. Depending on different particular patterns, the onepatterning process may include multiple exposing, developing, or etchingprocesses. Further, as an example, a particular pattern in the formedlayer structure may be continuous or discontinuous. As other example,these particular patterns may be at different heights or have differentthicknesses.

In an exemplary embodiment of the present disclosure, the second wiring151 may be electrically connected to the data line in the displayregion. Similarly, as an example, the data line may be disposed in thesame layer as the source/drain electrode 172 of the thin film transistorTFT. For example, the second wiring 151 may be electrically connected tothe data line via a via located in the second dielectric layer 160.

It should be noted that aspects of the data line mentioned above arewell known to those skilled in the art, and are not repeated herein.

In an exemplary embodiment of the present disclosure, the second powersignal line VSS may span the boundary 180″ of the third dielectric layer180 away from the display region AA. In addition, the second powersignal line VSS may partially surround the first power signal line VDDand a portion of the first via H1 and the second via H2.

FIG. 8 illustrates an enlarged schematic plan view of the portion cc′ inFIG. 2 in accordance with an embodiment of the present disclosure.Referring to FIGS. 2 and 8, FIG. 8 illustrates a portion of a planlayout of the peripheral region of the display substrate 10. Morespecifically, FIG. 8 illustrates a portion of a plan layout of the firstwiring region BB in the peripheral region of the display substrate 10.

Similar to the positional relationship shown in FIG. 7, the first powersignal line VDD may span a portion of the first via H1 and the secondvia H2.

In addition, in an exemplary embodiment of the present disclosure, ascan be seen from FIG. 8, the first power signal line VDD may also haveportions that do not span the first via H1 and the second via H2. Thatis, the first power signal line VDD may have a portion that extends fromthe boundary 180″ of the third dielectric layer 180 away from thedisplay region AA.

In an exemplary embodiment of the present disclosure, the first powersignal line VDD and the second power signal line VSS may extend beyondthe dam 300 along a direction away from the display region AA.

In an exemplary embodiment of the present disclosure, a boundary 250′ ofthe encapsulation layer 250 is located on a side of the dam 300 awayfrom the display region AA.

In an exemplary embodiment of the present disclosure, the first powersignal line VDD and the second power signal line VSS may extend beyondthe boundary 250′ of the encapsulation layer 250 along a direction awayfrom the display region AA.

In an embodiment of the present disclosure, a display device is alsoprovided. The display device may include the display substrate asdescribed above.

FIG. 9 illustrates a schematic plan view of a display device inaccordance with an embodiment of the present disclosure. As shown inFIG. 9, the display device 1 may include the display substrate 10.

In an exemplary embodiment of the present disclosure, the display device1 may be, for example, an OLED display device. As other examples, thedisplay device 1 may be, for example, a mobile phone, a tablet computer,a television, a display, a notebook computer, a navigator, a wearabledevice, an e-book reader, or the like.

The foregoing description of the embodiment has been provided forpurpose of illustration and description. It is not intended to beexhaustive or to limit the application. Even if not specifically shownor described, individual elements or features of a particular embodimentare generally not limited to that particular embodiment, areinterchangeable when under a suitable condition, can be used in aselected embodiment and may also be varied in many ways. Such variationsare not to be regarded as a departure from the application, and all suchmodifications are included within the scope of the application.

1. A display substrate, comprising: a substrate comprising a displayregion and a peripheral region surrounding the display region, theperipheral region comprising a first wiring region, the first wiringregion comprising a first sub-wiring region disposed along a firstdirection away from the display region; a first conductive layer locatedon the substrate, the first conductive layer comprising a first portionlocated in the peripheral region, the first portion of the firstconductive layer comprising a first wiring located in the first wiringregion; a first dielectric layer located on the first conductive layer;a second conductive layer located on the first dielectric layer, thesecond conductive layer comprising a first portion located in theperipheral region, wherein the first portion of the second conductivelayer comprises a second wiring located in the first wiring region, thefirst wiring and the second wiring being spaced apart from each otheralong a direction parallel to the substrate; a second dielectric layerlocated on the second conductive layer; a third conductive layer locatedon the second dielectric layer, the third conductive layer comprising afirst portion located in the peripheral region, wherein the firstportion of the third conductive layer comprises a third wiring locatedin the first wiring region; a third dielectric layer as a planarizationlayer located on the third conductive layer; a fourth conductive layerlocated on the third dielectric layer, the fourth conductive layercomprising a first portion located in the peripheral region, the firstportion of the fourth conductive layer comprising a fourth wiringlocated in the first sub-wiring region, wherein the fourth wiring iselectrically connected to the third wiring, an orthographic projectionof the fourth wiring on the substrate at least partially overlaps withan orthographic projection of the third wiring on the substrate.
 2. Thedisplay substrate according to claim 1, wherein the third dielectriclayer comprises a first via exposing the third wiring located in thefirst sub-wiring region, the fourth wiring is connected to the thirdwiring via the first via.
 3. The display substrate according to claim 2,wherein the third wiring and the fourth wiring constitute a first powersignal line.
 4. The display substrate according to claim 2, wherein thefirst via comprises a first array of first sub-vias and a second arrayof second sub-vias, the first sub-vias and the second sub-vias beingconfigured such that at least one of the first sub-vias is surrounded bythe second sub-vias closest to the at least one first sub-via, and atleast one of the second sub-vias is surrounded by the first sub-viasclosest to the at least one second sub-via.
 5. The display substrateaccording to claim 4, wherein at least one of the first sub-vias islocated at a center of a shape enclosed by the second sub-vias closestto the at least one first sub-via, and at least one of the secondsub-vias is located at a center of a shape enclosed by the firstsub-vias closest to the at least one second sub-via.
 6. The displaysubstrate according to wherein a cross-sectional shape of the first viaalong a plane parallel to the substrate comprises a truncated square,wherein a side of the truncated square has a length of 11 μm. 7.(canceled)
 8. The display substrate according to claim 2, wherein thefirst portion of the fourth conductive layer comprises a second viaexposing the third dielectric layer.
 9. The display substrate accordingto claim 8, wherein the second via comprises a first array of thirdsub-vias and a second array of fourth sub-vias, the third sub-vias andthe fourth sub-vias being configured such that at least one of the thirdsub-vias is surrounded by the fourth sub-vias closest to the at leastone third sub-via, and at least one of the fourth sub-vias is surroundedby the third sub-vias closest to the at least one fourth sub-via. 10.The display substrate according to claim 9, wherein at least one of thethird sub-vias is located at a center of a shape enclosed by the fourthsub-vias closest to the at least one third sub-via, and at least one ofthe fourth sub-vias is located at a center of a shape enclosed by thethird sub-vias closest to the at least one fourth sub-via.
 11. Thedisplay substrate according to claim 8, wherein a cross-sectional shapeof the second via along a plane parallel to the substrate comprises asquare, wherein a side of the square has a length of 16 μm. 12.(canceled)
 13. The display substrate according to claim 8, wherein atleast one of the first vias is located at a center of a shape enclosedby the second vias closest to the at least one first via, and at leastone of the second vias is located at a center of a shape enclosed by thefirst vias closest to the at least one second via.
 14. The displaysubstrate according to claim 13, wherein a spacing located between thefirst via and the second via is 6.5 μm in the first direction, a spacinglocated between the first via and the second via is 16.5 μm in a seconddirection parallel to the substrate and perpendicular to the firstdirection.
 15. The display substrate according to claim 1, furthercomprising a thin film transistor located in the display region, thethin film transistor comprising an active layer located on thesubstrate, a gate insulating layer located on the active layer, and agate located on the gate insulating layer, wherein the first conductivelayer further comprises a second portion located in the display region,the second portion of the first conductive layer comprising the gate ofthe thin film transistor, and wherein the third conductive layer furthercomprises a second portion located in the display region, the secondportion of the third conductive layer comprising a source/drainelectrode of the thin film transistor, the source/drain electrode beingconnected to a source/drain region of the active layer by passingthrough the first dielectric layer, the second dielectric layer, and thegate insulating layer, wherein the fourth conductive layer furthercomprises a second portion located in the display region, the secondportion of the fourth conductive layer being connected to thesource/drain electrode of the thin film transistor by passing throughthe third dielectric layer, wherein the display substrate furthercomprises a fourth dielectric layer as a planarization layer located onthe fourth conductive layer; and an encapsulation layer located on thefourth dielectric layer. 16-17. (canceled)
 18. The display substrateaccording to claim 15, further comprising a light emitting devicelocated in the display region and located between the fourth dielectriclayer and the encapsulation layer, the light emitting device comprisingan anode, a light emitting layer, and a cathode sequentially disposedalong a direction perpendicular to the substrate, wherein the anode islocated between the fourth dielectric layer and the encapsulation layer,and the anode is connected to the second portion of the fourthconductive layer via a via located in the fourth dielectric layer,wherein the display substrate further comprises a pixel definition layerdefining a light emitting region located between the fourth dielectriclayer and the encapsulation layer, the pixel definition layer having anopening exposing the anode.
 19. The display substrate according to claim18, wherein the first wiring region further comprises a secondsub-wiring region located on a side of the first sub-wiring region awayfrom the display region, wherein the display substrate further comprisesa dam located in the second sub-wiring region, the dam comprising afirst dam portion and a second dam portion sequentially spaced apartalong a direction away from the display region, wherein the first damportion comprises the fourth dielectric layer and the pixel definitionlayer, wherein the second dam portion comprises the third dielectriclayer, the fourth dielectric layer, and the pixel definition layer, andwherein the encapsulation layer sequentially covers the first sub-wiringregion and the dam in a direction parallel to the substrate and awayfrom the display region, and at least a portion of an edge of theencapsulation layer is located within the second sub-wiring region. 20.The display substrate according to claim 18, wherein the peripheralregion further comprises a bending region and a second wiring regionsequentially arranged in the first direction away from the displayregion and on a side of the first wiring region away from the displayregion, wherein the bending region has an opening passing through thegate insulating layer, the first dielectric layer, and the seconddielectric layer and exposing the substrate, and a planarization layercovering the opening, the planarization layer comprising at least one ofthe third dielectric layer and the fourth dielectric layer, and whereinthe second wiring region comprises the gate insulating layer, the firstdielectric layer, the second dielectric layer, the third conductivelayer, the fourth conductive layer, and the fourth dielectric layersequentially disposed on the substrate along a direction perpendicularto the substrate.
 21. The display substrate according to claim 3,further comprising a second power signal line located in the peripheralregion and surrounding the display region and the first power signalline, wherein the second power signal line comprises at least one of aportion of the third conductive layer located in the peripheral regionand a portion of the fourth conductive layer located in the peripheralregion, wherein the first power signal line is configured to provide afirst voltage, the second power signal line is configured to provide asecond voltage, and the first voltage is higher than the second voltage,and wherein the first power signal line further comprises a portionlocated in the second sub-wiring region, the bending region, and thesecond wiring region and disposed in the same layer as the thirdconductive layer and/or the fourth conductive layer.
 22. The displaysubstrate according to claim 1, further comprising a passivation layerlocated between the third conductive layer and the third dielectriclayer.
 23. The display substrate according to claim 8, wherein anorthographic projection of the first wiring on the substrate at leastpartially overlaps with an orthographic projection of the first via andthe second via on the substrate, and an orthographic projection of thesecond wiring on the substrate at least partially overlaps with anorthographic projection of the first via and the second via on thesubstrate. 24-25. (canceled)
 26. A display device comprising a displaysubstrate according to claim 1.